Generally, an image sensor is a semiconductor device for converting an optical image into an electric signal. There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices, hybrid focal plane arrays, etc. The various types of image sensors may be broadly categorized as charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensors.
CCDs are often employed for image acquisition and enjoy a number of advantages which makes it attractive for many small size imaging applications. CCDs are also produced in large formats with small pixel size and they employ low noise charge domain processing techniques.
However, CCD imagers suffer from a number of disadvantages. For example, CCDs are susceptible to radiation damage; CCDs are often expensive to manufacture; CCDs require good light shielding to avoid image smear and; CCDs have a high power dissipation for large arrays. CCD imagers also have a complicated driving method and a complicated fabrication process requiring a multi-phased photo process. A control circuit, a signal processing circuit, an analog to digital (A/D) converter circuit, etc., cannot be easily integrated into a CCD chip, thereby inhibiting the use of CCDs in compact size products. While there have been some attempts to integrate on-chip signal processing with a CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by linear charge transfers from pixel to pixel, requiring that the entire CCD array be read out into a memory before individual pixels or groups of pixels may be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.
Because of the inherent limitations in CCD technology, there has been increased interest in CMOS imagers for possible use as low cost imaging devices. CMOS image sensors first came to the fore in relatively low-performance applications where shuttering was not required, scene dynamic range was low, and moderate to high noise levels could be tolerated. A CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, star trackers, motion detection systems, image stabilization systems and high-definition television imaging devices.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCDs since standard CMOS processing techniques may be used. Additionally, CMOS imagers exhibit low power consumption because only one row of pixels at a time needs to be active during readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
FIGS. 1A and 1B are cross-sectional views of conventional CMOS pixels known as 3T pixels (for three-transistor pixel) and 5T pixels (for 3-transistor plus 2-transfer gate pixel). More precisely, the 3T pixel 10 of FIG. 1A (designated hereinafter an n—3TPPD pixel) includes three NMOS transistors 12, 14, 16 standing for a reset transistor 12, a source follower transistor 14 and a row transistor 16. The reset transistor 12 is electrically connected to a sense node 18. The sense node 18 is formed of an n+ contact 22 and a pinned photodiode 20. The pinned photodiode 20 includes a thin p-type pinning layer 26 overlying a custom n-diode implant 24, that in turn, overlies and forms a depletion region with a p-epitaxial layer 30. A p-substrate 32 underlies the p-epitaxial layer 30. A p-well 34 is formed adjacent the pinned photodiode 20 in the p-epitaxial layer 30 for isolating the n—3TPPD pixel 10 from neighboring pixels. A p+ return contact 36 is formed proximal to the other side of the pinned photodiode 20 and is held at ground potential (about 0V) for providing a return and ground reference for the n—3TPPD pixel. A p-well 38 is formed adjacent to the p+ return contact 36.
When operated, a CLOCK applied to the gate of the reset transistor 12 causes a reverse bias on the pinned photodiode 20. The source follower transistor 14 and the row transistor 16 are coupled between a drain supply VDD of about 3.3V and an output signal terminal COLUMN VIDEO. The drain of the reset transistor 12 is connected to VDD; the gate of the reset transistor 12 is connected to a RESET clock; and the source of the reset transistor is connected to the cathode of the pinned photodiode 20 so that the reset transistor 12 operates as a source follower. The source of the source follower transistor 14 is connected to the drain of the row transistor 16, and the source of the row transistor 16 is connected to output terminal COLUMN VIDEO. In applications, a plurality of such 3T pixels is coupled to the same output terminal COLUMN VIDEO. By selectively applying row address signal ROW SELECT to the gate of the selected row transistor 16, different rows may be coupled to the output terminal COLUMN VIDEO (i.e., a column bus).
The 5T pixel 40 (FIG. 1B), also known as a charge transfer pixel (designated hereinafter an n—5TPPD pixel), is similar to the 3T pixel 10 (FIG. 1A) except that the 5T pixel 40 has a transfer gate 42 coupled between the reset transistor 12 and the pinned photodiode 20 so that a sense node 44 may be created between the transfer gate 42 and the reset transistor 12. The sense node 44 may be isolated from the pinned photodiode 20. As a result, charge may be transferred from a photodetection region to the sense node 44 when a positive voltage (preferably a “logical 1” or “high” positive voltage of about 3.3V) is applied to the input TRANSFER GATE 1, where a resulting voltage is read out by the source follower transistor 14.
The 5T pixel 40 also includes a second transfer gate 46 abutting the side of the pinned photodiode 20 distal to the transfer gate 42. An n+ contact 48 is formed adjacent to the second transfer gate 44 distal to the pinned photodiode 20 and is also tied to VREF (about +3.3 volts). The second transfer gate 44 may be used as a global reset for the imager and as an antiblooming gate for preventing excess charge generated in the photodiode 20 from “blooming” through the transfer gate 42 to the sense node 44 when a voltage is applied to the input TRANSFER GATE 2 that is more positive than the transfer gate-to-sense node voltage.
Similar 4T and 6T CMOS pixel designs are also known. The n—3TPPD and n—5TPPD and similar n—4TPPD and n—6TPPD pixels are hereinafter designated as n_pixels.
High performance for both CCD and CMOS imagers implies at least very low read noise (1-4 e−), high quantum efficiency (transmission limited), deep depletion for near IR and soft x-ray charge collection efficiency (CCE) performance, low pixel cross talk (high MTF), high charge transfer efficiency (CTE), high signal-to-noise ratio for low contrast scenes and very high speed/low noise parallel readout using integrated designs.
In a CCD imager, the electronic circuitry and gates are formed on one side of a silicon wafer, i.e., the front side; the other side of the wafer is the back side. When a CCD imager is illuminated on the front side, absorption of incident light by the electronic circuitry reduces quantum efficiency. As an alternative, CCDs may be illuminated from the back side; however, back side illumination produces other problems. When incident photons enter the back side of the CCD imager, they are absorbed in a silicon substrate and produce electronic charge by the photoelectric effect. Wafer thickness of the CCD imager must be sufficient to allow charge generation, and a depletion region should exist to transport the charge to collecting channels. For conventional low resistivity substrates, the thickness of the depletion region is limited to less than about 5 μm. Therefore, for good blue and ultraviolet response, the substrate must be extremely thin in order to have acceptable charge spreading (crosstalk), resulting in a very fragile and expensive structure.
Therefore, it is desirable to implement a back side illuminated CCD imager that has a thick substrate, and which has a high quantum efficiency over a broad range of wavelengths, from infrared and red to blue and ultraviolet.
U.S. Pat. No. 6,259,085 (hereinafter “the '085 patent”) discloses a back side illuminated CCD imager formed of a relatively thick high resistivity photon sensitive silicon substrate, with frontside electronic circuitry, and an optically transparent back side ohmic contact for applying a back side voltage which is at least sufficient to substantially fully deplete the substrate. A bias voltage which overdepletes the substrate may also be applied. One way of applying the bias voltage to the substrate is by physically connecting the voltage source to the ohmic contact. An alternate way of applying the bias voltage to the substrate is to physically connect the voltage source to the front side of the substrate at a point outside the depletion region. Thus both front side and back side contacts may be used for back side biasing to fully deplete the substrate.
Compared to CCDs, low pixel cross talk is more difficult to achieve for the CMOS imagers described in the '085 patent, especially for thick imagers that detect near IR and x-ray photons. For these sensors, high resistivity epitaxial silicon is also required for deep depletion and good charge collection efficiency (CCE). However, even when silicon is fully depleted, the desired low cross talk may not be realized. Hence, as with CCD imagers, it is desirable to apply an additional bias voltage across the imager in the form of substrate bias to deal with the cross talk problem (other than just employing high substrate resistivity). Following how very deep depletion CCDs handled the CCE problem as described in the '085 patent, substrate bias may also significantly improve cross talk performance for CMOS imagers. However, the technique is considerably more difficult to implement in CMOS compared to CCDs.
Accordingly, what would be desirable, but has not yet been provided, is a fully implemented CMOS imager that effectively employs substrate bias to reduce or eliminate cross talk.